When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA

Description of When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA

GitHub Link

The GitHub link is https://github.com/os-hxfan/bayesnn_fpga

Introduce

This GitHub repository, titled "FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks," offers a FPGA-based accelerator for implementing dropout-based Bayesian Neural Networks (BayesNNs). The repository supports multi-exit Monte Carlo Dropout (MCD) and multi-exit Masksembles on FPGA. It contains software artifacts for evaluating accuracy and ECE, as well as hardware artifacts for assessing the proposed FPGA-based accelerator's performance. The software is based on PyTorch, while the hardware implementation utilizes HLS4ML and QKeras. The repository provides code, models, datasets, and tools for both software and hardware evaluation. Detailed setup instructions are available in the README files. The associated paper is titled "When Monte-Carlo Dropout Meets Multi-Exit Optimizing Bayesian Neural Networks on FPGA," authored by Fan et al. and presented at the 60th ACM/IEEE Design Automation Conference in 2023. Bayesian Neural Networks (BayesNNs) have demonstrated their capability of providing calibrated prediction for safety-critical applications such as medical imaging and autonomous driving.

Content

FPGA-based hardware acceleration for dropout-based Bayesian Neural Networks (BayesNNs). We support both multi-exit Monte Carlo Dropout (MCD) and multi-exit Masksembles on FPGA. This repo contains the artifacts of our DAC'23 paper and TCAD'23 submission. Pls cite us if you found it helpful. The software is based on Pytorch, and the hardware implementation is based on HLS4ML and QKeras. Pls cite our paper and give this repo _ if you feel the code and paper are helpful! Our paper is online now (link)! If you found it helpful, pls cite us using:

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